Technical Field
The present invention generally relates to a structure and manufacturing of power field effect transistors, and specifically relates to a trench gate power metal oxide semiconductor field effect transistor (MOSFET) and a trench gate insulated gate bipolar transistor (IGBT).
Related Art
The present invention will be described in an n channel power FET, but it will be appreciated in the following description that the present invention is also applicable to a p channel power FET. In the specification of the present invention, heavily doped n-type regions are labeled as n+ and heavily doped p-type regions are labeled as p+. These heavily doped regions usually have a doping concentration of between 1×1018 cm−3 and 1×1021 cm−3. On the other hand, lightly doped n-type regions are labeled as n- and lightly doped p-type regions are labeled as p−. These lightly doped regions usually have a doping concentration of between 1×1013 cm−3 and 1×1017 cm−3.
Low-voltage power MOSFETs have been widely used in switch mode power supplies (e.g. DC-DC converters). For example, a central processing unit (CPU) in the current advanced technology needs a DC-DC converter, which provides high output current of about 10 A and low output voltage simultaneously. In order to obtain high efficiency in the converter, the power MOSFET here should have extremely low on-resistance. The important component part of the on-resistance of the low-voltage power MOSFET is the channel resistance. Therefore, a trench gate structure is usually used in the low-voltage power MOSFET to provide a larger channel density than that of a planar structure. In addition, the cell pitch of the trench gate power MOSFET needs to be reduced to increase the channel density. Therefore, the object of the present invention is to provide a low-voltage trench gate power MOSFET with a small cell pitch and therefore a low on-resistance. Also, the small cell pitch is also desirable in a trench gate IGBT structure, because the small cell pitch can achieve injection enhancement near an emitter and thus decrease the on-state voltage drop. Therefore, another object of the present invention is to provide a trench gate IGBT with low on-state voltage drop.
In addition to the on-resistance demand, the trench gate power MOSFET (TMOS) also needs to have high reliability. For example, due to the activation of the parasitic BJT in this device, the device should not fail during the unclamped inductive switching (UIS). Therefore, yet another object of the present invention is to provide a TMOS with improved UIS strength. In addition, the activation of the parasitic BJT in the IGBT should also be prevented to realize latch-up free of the device. Therefore, yet another object of the present invention is to provide a latch-up free trench gate IGBT.
The cross section of a TMOS structure in the prior art is shown in FIG. 1. The channels of the device are positioned on the side wall surface of a p-type body region (13), and an n+ source region (11) and an n-epi (14) are connected through the channels in the on-state. The on-resistance of the device is mostly dependent on the cell pitch of the device. A small cell pitch is required to realize a high channel density and therefore a low channel resistance.
The cross section [1] of a trench gate TMOS structure in the prior art is shown in FIG. 2. As shown in the figure, an interlayer dielectric (ILD) (32) is positioned on the top of a gate electrode (21) in a trench, and the gate electrode (21) is isolated from a source electrode (22) by the ILD (32). As compared with the structure shown in FIG. 1, the width of the n+ source region (11) can be reduced, because there is no a lateral space between the source contact holes and the gate electrode (21) in the trench gate TMOS. The reduced cell pitch can result in a reduced on-resistance compared with the structure shown in FIG. 1. However, a complicated deposition and deep etching process is required to form the ILD (32) in the device.
In the device structures shown in FIG. 1 and FIG. 2, an advanced photolithography technology can be used to reduce the cell pitch without changing the structures. However, the reduced cell pitch in those structures can also result in the reduced contact area of the n+ source region (11) and the source electrode (22), and the contact resistance here will increase. Due to such restriction, even if the advanced photolithography technology is used, the on-resistance of those devices still cannot be reduced a lot. In order to mitigate contact problems, a buried gate TMOS structure has been proposed, as shown in FIG. 3 [2]. However, in the buried gate structure, the contact area is still restricted by the cell pitch, and contact problems cannot be solved completely.
In order to solve the contact problem at the source, a trench-shaped source contact hole TMOS structure [3] is proposed. The cross section of the trench-shaped source contact hole TMOS structure is shown in FIG. 4. In this structure, the n− source region (11) contacts the source electrode (22) at the side wall of the trench-shaped contact hole. The contact area at the source is not restricted by the cell pitch, and the contact area is only determined by the depth of the n− source region (11), instead of the width of the n+ source region (11). This structure enables the device to be manufactured with the advanced photolithography technology, and the contact resistance at the source will not be increased. However, the structure needs a deep n+ source region (11) to provide a big source contact area, but a shallow n+ source region (11) is generally used in the structure to obtain an approximately uniform doping profile in the p-type body region (13). As shown in the figure, the p-type body region (13) is positioned below the n+ source region (11), and for reducing the channel resistance, the uniformly doped p-type body region (13) is desirable [4]. Both the p-type body region (13) and the n+ source region (11) are usually formed by ion implantation and annealing. In the case of the shallow n− source region (11), the approximately uniform doping profile in the p-type body region (13) can be obtained through multiple times of low-energy ion implantation, because the standard deviation of these implanted projected ranges is relatively small. However, if the n+ source region (11) is relatively deep, high-energy ion implantation is required to form the p-type body region (13), and it is difficult to realize approximately uniform doping profile due to the relatively large standard deviation of the implanted projected range. Due to the shallow n+ source region (11) used in the structure, compared with these structures previously shown in FIG. 1, FIG. 2 and FIG. 3, the contact resistance at the source cannot be reduced a lot.